Multi-Core and Many-Core Processors

Quoting the following information from http://www.argondesign.com

Single Core

Processors were originally developed with only one core, executing one thread at a time. Programmers regularly employ "multithreading" to allow the processor to switch between threads giving the impression that the threads are running concurrently, although the tasks can only be processed one at a time. The only way to improve processing throughput is to run the core faster which requires more energy.

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MultiCore

A multicore processor is typically made up of two, four, six or eight independent processor cores in the same silicon connected through an on-chip bus, a central intersection through which all information must flow between processor cores or between cores and memory and I/O. Multicore processors do execute threads concurrently, typically boost performance in compute intensive processes and will use less power than coupling multiple single-core processors. However as more cores are added the on-chip bus creates an information traffic jam as all the data must travel through the same path, limiting the benefits of multiple cores.

ManyCore

A manycore processor is one in which the number of cores is large enough that traditional multi-processor techniques are no longer efficient, such processors will either be more application specific or require a different approach. Tilera addresses the multi-processor scalability problem with a revolutionary new chip architecture that can harness the processing power of hundreds of cores on a single chip, see Tilera Technology; Tilera provides general purpose manycore processors with 16 to 100 identical processor cores (tiles) interconnected with Tilera's iMesh™ on-chip network.

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Increasingly, applications demand more and more compute power. For now, we see this type of novel chip architecture used in High Performance Computing. However, it's not hard to imagine these more powerful processors make their way into handheld devices, smartphones and tablets, provided that we can write software to make efficient use of these new chip architectures.